The present invention relates to the processing of semiconductors, as, for example, in the fabrication of microelectronic devices and other micro-scale and nano-scale structures.
The patterning of semiconductor materials through etching is performed almost universally in the fabrication of microelectronic circuits and devices, as well as certain semiconductor elements and substrates used to interconnect microelectronic devices. The constant demand on the microelectronics industry to increase the speed and density of integrated circuits require that the dimensions of at least some microelectronic devices be reduced from one generation to the next.
However, as device sizes are reduced, difficulties are encountered in maintaining new device dimensions within tolerances. This is especially true of the critical dimension of a device. In integrated circuits, the critical dimension represents the smallest size of certain features, such as an element of a transistor. For example, the width of the gate conductor of a field effect transistor (FET) of an integrated circuit is generally fabricated to the critical dimension. Other features of a FET, such as the source and drain, may also need to be fabricated at the critical dimension. As these device elements are reduced in size, the difficulty of patterning them increases. The challenges of etching semiconductor materials to the correct physical dimensions is a growing concern.
The formation of gate conductors of FETs poses particular challenges. In some processes, a layer of intrinsic polysilicon, or at most lightly doped polysilicon, is deposited to a thickness of about 1500 Å on a gate dielectric. Thereafter, heavily doped p+ and n+ regions are formed in the uppermost 250 Å to 500 Å thickness of the layer by implanting dopants of respective types (e.g., boron as a p+ dopant, and phosphorous as an n+ dopant) in separate masked implantations. This results in a layered stack having a lower layer of intrinsic, or at most lightly doped, polysilicon and an upper layer of heavily doped polysilicon. The layered stack is then patterned by etching down to the gate dielectric to define the locations and widths of the gate conductors. Subsequent high temperature annealing then drives dopants from the upper polysilicon layer into the lower polysilicon layer to form p doped gate conductors of p-type FETs and n doped gate conductors of n-type FETs.
The patterning of the layered stack is performed efficiently when both the upper layer and the lower layer are patterned together by etching. However, heretofore, the patterning of a heavily doped polysilicon layer and an intrinsic or lightly doped polysilicon layer has posed difficulties for maintaining the critical dimension of the gate conductor.
FIG. 1 illustrates a problem of patterning both a heavily doped polysilicon layer and an essentially undoped layer according to the prior art. As illustrated in FIG. 1, an upper, heavily doped, polysilicon layer 37 (illustratively, n+ doped) is disposed above a lower, lightly doped (or not doped), lower polysilicon layer 39. In turn, the lower polysilicon layer 39 is disposed on a gate dielectric 30 (here, a gate oxide layer). In this example, the dopant concentration in the upper layer illustratively ranges from about 1018 cm−3 to 1021 cm−3, while the dopant concentration in the lower layer is typically below 1016 cm−3, and more commonly below 10 15 cm−3. The lower polysilicon layer 39 is not required to have any dopants present.
Thus, the upper layer has a dopant concentration that is two or more orders of magnitude higher than that of the lower layer. The upper and lower layers 37, 39 are parts of a gate conductor stack. The upper and lower layers 37, 39 are shown here after etching by a conventional single-step anisotropic vertical etch process, such as any of several known classes of directional etching processes, e.g., a reactive ion etch (RIE). Illustratively, the gate dielectric is a gate oxide, such as provided by thermal growth from an uppermost device region (not shown) of a semiconductor substrate (not shown). The substrate is typically a bulk substrate or semiconductor-on-insulator type substrate having a device region including silicon and/or silicon germanium.
The developed patterns of a photoresist imaging layer are shown as layer 35, and layer 36 is an anti-reflective coating (ARC) or other hardmask material (hereinafter “ARC layer”) that is patterned according to the image patterns in the photoresist layer. ARC layer 36 helps to transfer the photoresist image patterns to the polysilicon layers 37 and 39 underlying it.
In an exemplary etching process according to the prior art, component gases present in the etching chamber include SF6, NF3 or HBr or a mixture thereof. As apparent from FIG. 1, the sidewall of the upper layer 37 has eroded significantly, such that the sidewalls 38 of the upper layer 37 are not straight. Rather, the sidewalls 38 have been undercut underneath the ARC layer 36. As a result, the dimension 40 of the bottom surface 33 of the upper layer 37 has become smaller than the dimension 42 at the top surface 34. While the lower layer 39 is potentially subject to some erosion and undercutting during etching, this problem affects the upper layer 37 disproportionately, because of its much higher dopant concentration (by orders of magnitude). Other etching mixtures are also problematic. For example, when the etchant includes NF3 mixed with a fluorocarbon having a low carbon to fluorine ratio (e.g. CF4), results are detrimental to the photoresist mask 35. A mixture of CF4 and SF6 has also been tried for etching heavily doped polysilicon. However, this chemistry has resulted in severe etch depth non-uniformity within the wafer when etching heavily doped polysilicon, which can impact the integrity of the patterned structures.
The effect of the problem is experienced most when the lower layer of polysilicon 39 is etched. Since the eroded upper layer 37 has a smaller dimension 40 than desired, this smaller dimension 40 is transferred to the critical dimension 44 of the lower layer 39 during etching. As a result, the critical dimension 44 of the gate conductor in contact with the gate oxide 30 becomes smaller than the desired dimension 42. Stated another way, the erosion of the upper layer 37 prevents the desired dimension 42 of the patterned ARC layer 36 from being transferred faithfully to dimension 44 of the lower layer 39 where the lower layer meets the gate oxide 30.
Thus, a solution is needed for etching a region of heavily doped semiconductor material to produce a patterned region having straight sidewalls, which avoids substantial sidewall erosion and undercutting. Having produced a patterned region having straight sidewalls, a region of lightly doped semiconductor material lying below the patterned region could itself be patterned more reliably to an intended dimension.